The present invention relates to a dynamic random access memory (DRAM) cell capacitor. More particularly, the present invention relates to a method for manufacturing the a memory cell capacitor having increased capacitance by forming an Hemi-Spherical Grain (HSG) layer on a surface of a memory cell storage electrode.
As DRAMs increase in memory cell density, the space allocated for each memory cell of the DRAM decreases. This result continuously challenges DRAM designers, since memory cell capacitance decreases with area, all other conditions remaining constant. Many efforts have been made to maintain memory cell capacitance at a sufficiently high storage capacitance, despite decreasing memory cell size.
For example, U.S. Pat. No. 5,385,863 issued Jan. 31, 1995 to Tatsumi entitled "METHOD OF MANUFACTURING POLYSILICON FILM INCLUDING RECRYSTALLIZATION OF AN AMORPHOUS FILM," discloses a conventional DRAM cell capacitor structure and manufacturing method for same. The reference is incorporated herein by reference. As shown this reference, HSG silicon is grown on a capacitor storage electrode having a simple "staked" structure in order to increase capacitance per unit area of the memory cell.
FIG. 1 shows a conventional DRAM cell capacitor. Referring to FIG. 1, the DRAM cell capacitor includes a semiconductor substrate 10 having active and inactive regions as defined by a field oxide layer 12. A pad electrode 14 is formed on the active region of substrate 10. An interlayer insulating layer 16 (with component portions 16a and 16b) is formed over field oxide layer 12 and pad electrode 14. A contact hole 19 is formed through interlayer insulating layer 16 to an upper surface of pad electrode 14. A conductive layer is then deposited on interlayer insulating layer 16 to fill contact hole 19. The conductive layer is then patterned to form a capacitor storage electrode 20. As storage electrode 20 is formed, an upper surface of the storage electrode 20 is perpendicular to each of its sidewalls.
Next, an HSG silicon layer 22 is formed on capacitor storage electrode 20 to increase an effective surface area. Subsequently, so as to accomplish fabrication of the DRAM cell capacitor, the process steps for sequentially forming a dielectric layer and a capacitor plate electrode on the capacitor storage electrode are performed.
Prior to forming the dielectric layer (not shown) over storage electrode 20, a wet etching and washing process are performed to remove a portion of interlayer insulating layer 16b and to prepare the surface. Generally, the etching process of interlayer insulating layer 20 uses an enchant that includes a mixture of NH.sub.4 F and HF (which is called a "La1 solution" in the art), and a mixture of NH.sub.3, H.sub.2 O.sub.2 and deionized water (which is called an "SC-1 solution"), and the washing process uses an enchant that is a mixture of the SC-1 solution and HF.
During the etching process using the SC-1 solution, a portion of HSG silicon layer 22 which is formed on storage electrode 20, i.e., the portion on the top edges of storage electrode 20, is susceptible to lifting. When this happens, adjacent capacitor storage electrodes may be electrically connected 24 (i.e., short-circuited) one to another by the lifted HSG silicon. More particularly, lifting of the HSG silicon from the storage electrode is caused by at least one of the following reasons: (1) HSG silicon which has abnormally grown due to the remaining polymers is lifted during the etching process of the storage electrode, and/or (2) HSG silicon grown on the top edges of the storage electrode is lifted by the subsequent etching and washing processes.
A short-circuit of adjacent storage electrodes due to the lifted HSG silicon is shown in FIGS. 2A and 2B. FIG. 2A is a scanning electron microphotograph (SEM) showing a plan view of a conventional DRAM cell capacitor array. FIG. 2B is a SEM showing a perspective view of the conventional DRAM cell capacitor array shown in FIG. 2A. As is apparent from FIGS. 2A and 2B, after formation of the storage electrodes, a short-circuit between adjacent storage electrodes is formed by HSG silicon which has lifted from the top edges of the respective storage electrodes. This leads to the failure of the DRAM devices.